Papers_Lecture Proceedings »
Multiplier-less 1-Level Discrete Wavelet Transform Implementations on ZC206 development kit
In this paper, we investigate the design and implementation aspects of 1-level DWT by employing a finite impulse response (FIR) filter on FPGA platform. We estimate the performance requirements and hardware resources for two key multiplication-free architectures, namely, distributed arithmetic algorithm (DAA) and residue number system (RNS), allowing for selection of the proper algorithm and implementation of DAA and RNS-based DWT. The design has been implemented and synthesized in Xilinx Virtex-6 ML605 FPGA, taking advantage of Virtex-6’s embedded block RAMs (BRAMs). The results show that the DAAbased approach is appropriate and feasible for a small number of filter taps, while the RNS-based approach would be more appropriate for more than 10 filter taps.